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| 1 of 14 011006 features two linear taper potentiometers ds1845-010 one 10k, 100 position & one 10k, 256 position ds1845-050 one 10k, 100 position & one 50k, 256 postition ds1845-100 one 10k, 100 position & one 100k, 256 position 256 bytes of eeprom memory access to data and potentiometer control via an i 2 c compatible 2-wire interface external write enable pin to protect data and potentiometer settings nonvolatile wiper storage operates from 3v or 5v supplies packaging: flip chip package, 16-ball csbga, 14-pin tssop industrial operating temperature: -40oc to +85oc 16-ball csbga (4mm x 4mm) 14-pin flip chip (100-mil x 100-mil) ( not shown) description the ds1845 dual nv potentiometer and memory consists of one 100-position linear taper potentiometer, one 256-position linear taper potentiometer, 256 by tes of eeprom memory, and a 2-wire interface. the device provides an ideal method fo r setting bias voltages and currents in control applications using a minimum of circuitry. the eeprom memory allows a user to store configuration or calibration data for a specific sy stem or device as well as provide control of the potentiometer wiper settings. any type of user information may reside in the first 248 bytes of this memory. the next two addresses of eeprom memory are for potentiometer settings. access to this eeprom is via an industry standard 2-wire bus. the wiper position of the ds1845, as well as eeprom data, can be hardware write-protected using the write protect (wp) input pin. up to eight ds1845s can be installed on a single 2-wire bus. access to an individual devi ce is achieved by using a device address that is determined by the logic levels of address pins a0 though a2. additionally, the ds1845 will operate from 3 volt or 5 volt supplies. three package options are available: flip chip package, 16-ball csbga and 14-pin tssop. ds1845 dual nv potentiomete r and memory www.maxim-ic.com sda 1 14 vcc scl 2 13 h0 a0 3 12 w1 a1 4 11 h1 a2 5 10 l1 wp 6 9 w0 gnd 7 8 l0 14-pin tssop (173 mil) a b c d 1 2 3 4 top view
ds1845 2 of 14 pin descriptions name tssop bga description v cc 14 a3 power supply terminal. the ds1845 will support supply voltages ranging from +2.7v to +5.5v. gnd 7 d1 ground terminal. sda 1 b2 2-wire serial data interface. the serial data pin is for serial data transfer to and from the ds1845. the pin is open drain and may be wire-ored with other ope n drain or open collector interfaces. scl 2 a2 2-wire serial clock input. the serial clock input is used to clock data into the ds1845 on risi ng edges and clock data out on falling edges. wp 6 c1 write protect input. if set to logic 0, the data in memory and the potentiometer wiper setting may be changed. if set to logic 1, both the memory and the potentiometer wiper settings will be write protected. the wp pin is pulled high internally. a0 3 a1 address input. pins a0, a1, and a2 are used to specify the address of each ds1845 when used in a multi-dropped configuration. up to eight ds1845s may be addressed on a single 2-wire bus. a1 4 b1 address input. a2 5 c2 address input. h0 13 a4 high terminal of potentiometer 0. for both potentiometers, it is not required that the high termin al be connected to a potential greater than the low terminal. voltage applied to the high terminal of each potentiometer cannot exceed v cc or go below ground. h1 11 b3 high terminal of potentiometer 1. l0 8 d3 low terminal of potentiometer 0. for both potentiometers, it is not required that the low terminal be connected to a potential less than the high terminal. voltage applied to the low terminal of each potentiometer cannot exceed v cc or go below ground. l1 10 c4 low terminal of potentiometer 1. w0 9 d4 wiper terminal of pot 0. the wiper position of potentiometer 0 is determined by the byte at eeprom memory location f9h. voltage applied to the wipe r terminal of each potentiometer cannot exceed the power supply voltage, v cc , or go below ground. w1 12 b4 wiper terminal of pot 1. the wiper position of potentiometer 1 is determined by the byte at eeprom memory location f8h. nc c3 no connect. nc d2 no connect. ds1845 3 of 14 ds1845 block diagram figure 1 memory organization the ds1845?s serial eeprom is internally organized with 256 words of 1 byte each. each word requires an 8-bit address for random word addressing. the byte at address f9h determines the wiper setting for potentiometer 0, which contains 100 positions. writing valu es above 63h to this addr ess sets the wiper to its uppermost position. the byte at address f8h dete rmines the wiper setting for potentiometer 1, which contains 256 positions (00h to ffh). the factory defa ult wiper position for both potentiometers is ffh. memory locations 00h to f7h are factory programme d to 00h. address locations fah though ffh are reserved and should not be written. device operation clock and data transitions: the sda pin is normally pulled high with an external resistor or device. data on the sda pin may only change during scl low time periods. data changes during scl high periods will indicate a start or stop conditions depending on the conditions discussed below. refer to the timing diagram fig 2 for further details. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command. refer to the timing diagram fig 2 for further details. stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command places the ds1845 into a low-power mode. refer to the timing diagram fig 2 for further details. acknowledge: all address and data byte ar e transmitted via a serial pr otocol. the ds1845 pulls the sda line low during the ninth clock pulse to acknowledge that it has received each word. standby mode: the ds1845 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the comp letion of all inte rnal operations. vcc gnd sda scl wp a0 a1 a2 h0 w0 l0 h1 w1 l1 248 bytes eeprom memory 6 reserved bytes 1 byte wiper setting pot 0 1 byte wiper setting pot 1 control data potentiometer 0 2-wire interface potentiometer 1 100 position pot 256 position pot ds1845 4 of 14 2-wire interface reset: after any interruption in protocol, power loss, or system reset, the following steps reset the ds1845. 1. clock up to nine cycles. 2. look for sda high in each cycle while scl is high. 3. create a start condition while sda is high. device addressing: the ds1845 must receive an 8-bit device a ddress word following a start condition to enable a specific device for a read or write oper ation. the address word is clocked into the ds1845 msb to lsb. the address word consists of ah (1010) followed by a2, a1, and a0 then the r/w (read/write) bit. if the r/w bit is high, a read operation is initiated. the r/w is low, a write operation is initiated. for a device to become active, the values of a2, a1 and a0 must be the same as the hard-wired address pins on the ds1845. upon a match of written and hard -wired addresses, the ds1845 will output a zero for one clock cycle as an acknowledge. if the address does not match the ds1845 returns to a low-power mode. write operations: after receiving a matching address byte with the r/w bit set low, the device goes into the write mode of operation. the master must transmit an 8-b it eeprom memory address to the device to define the address where the data is to be written. after the reception of this byte, the ds1845 will transmit a zero for one clock cycle to acknowledge th e receipt of the address. the master must then transmit an 8-bit data word to be written into this address. the ds1845 will again transmit a zero for one clock cycle to acknowledge the receipt of the data. at this point the master must terminate the write operation with a stop condition. the ds1845 then enters an internally timed write process t w to the eeprom memory. all inputs are disabled during this byte write cycle. the ds1845 is capable of an 8-byte page write. a pa ge write is initiated the sa me way as a byte write, but the master does not send a stop condition after the 1 st byte. instead, after the slave acknowledges receipt of the data byte, the master can send up to seven more bytes using the same nine-clock sequence. the master must terminate the write cycle with a stop condition or the data clocked into the ds1845 will not be latched into permanent memory. acknowledge polling: once the internally-timed write has star ted and the ds1845 inputs are disabled, acknowledge polling can be initiated. the process involves transmitting a start condition followed by the device address. the r/w bit signifie s the type of operation that is de sired. the read or write sequence will only be allowed to proceed if the internal wr ite cycle has completed and the ds1845 responds with a zero. read operations: after receiving a matching address byte with the r/w bit set high, the device goes into the read mode of operation. there are three read operations: current address read, random read and sequential addr ess read. ds1845 5 of 14 current address read the ds1845 has an internal address regi ster that maintains the address us ed during the last read or write operation, incremented by one. this data is maintained as long as v cc is valid. if the most recent address was the last byte in memory, then the register resets to the first address. this address stays valid between operations as long as power is available. once the device address is clocked in and acknowledged by the ds1845 with the r/w bit set to high, the current address data word is cloc ked out. the master does not respond with a zero, but does generate a stop condition afterwards. random read a random read requires a dummy byte write sequence to load in the data word address. once the device and data address bytes are clocke d in by the master, and acknowledged by the ds1845, the master must generate another start condition. the master now initia tes a current address read by sending the device address with the read/write bit set high. the ds 1845 will acknowledge the device address and serially clocks out the data byte. sequential address read sequential reads are initiated by either a current address read or a random address read. after the master receives the first data byte, the ma ster responds with an acknowledge. as long as the ds1845 receives this acknowledge after a byte is read, the master may clock out additional data words from the ds1845. after reaching address ffh, it resets to address 00h. the sequential read operation is terminated when th e master initiates a stop c ondition. the master does not respond with a zero. for a more detailed description of 2-wire theo ry of operation, refer to the following section. 2-wire serial port operation the 2-wire serial port interface supports a bi-dir ectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is ca lled a ?master.? the devices that are controlled by the master are ?slaves.? the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates th e start and stop conditions. the ds1845 operates as a slave on the two-wire bus. connections to the bus are made via the open-drain i/o lines sda and scl. the following i/o terminals control the 2-wire serial port: sda, scl, a0, a1, a2. timing diagrams for the 2-wire serial port can be found in figures 2 and 3. timing information for the 2-wire serial port is provided in the ac electrical characteristic s table for 2-wire se rial communications. the following bus protocol has been defined: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. ds1845 6 of 14 start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid da ta when, after a start condition, the data line is stable for the duration of the high period of th e clock signal. the data on the line can be changed during the low period of the clock signal. there is one clock pulse per bit of data. figures 2 and 3 detail how data transfer is accomplished on the two- wire bus. depending upon the state of the r/w bit, two types of data transfer are possible. each data transfer is initiated with a start c ondition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferre d byte-wise and each receiver acknowledges with a 9 th bit. within the bus specifications a regular mode (100 kh z clock rate) and a fast mode (400 khz clock rate) are defined. the ds1845 works in both modes. acknowledge: each receiving device, when addressed, is ob liged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowle dge related clock pulse. of course, setup and hold times must be taken into acc ount. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to en able the master to gene rate the stop condition. 1. data transfer from a master transmitter to a slave receiver. the 1 st byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the master transmits the 1 st byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? can be returned. the master device generates all se rial clock pulses and the start an d stop conditions. a transfer is ended with a stop condition or with a repeated st art condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. ds1845 7 of 14 the ds1845 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl respectively. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave (device) address and direction bit. 2. slave transmitter mode: the 1 st byte is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1845 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address: command/control byte is the 1 st byte received following the start condition from the master device. the command/control byte consists of a 4-bit control code. for the ds1845, this is set as 1010 binary for read/write operations. the next 3 bits of the command/ control byte are the device select bits or slave address (a2, a1, a0). they are used by the master device to select which of eight devices is to be accessed. when reading or writing the ds1845, the device-select bits must match the device-select pins (a2, a1, a0). the last bit of the command/contro l byte (r/w) defines the operation to be performed. when set to a 1 a read operation is selected, a nd when set to a 0 a write operation is selected. following the start condition, the ds1845 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. write protect an external pin wp (write prot ect) protects eeprom data and poten tiometer position from alteration in an application. this pin must be open or tied high to protect da ta from alteration. reading and writing the potentiometer values reading from and writing to the potentiometers consists of a standard read or write to eeprom memory at the addresses f8h and f9h. the 8-bit value at a ddress f9h controls the wi per setting for potentiometer 0, which has 100 positions. the 8-bit value at address f8h controls th e wiper setting of potentiometer 1, which has 256 positions. potentiometer 1 may be set to any value between 00h and ffh. 00h sets the wiper of potentiometer 1 to its lowest value and ffh sets the wiper to its highest. potentiometer 0 may be set to any value between 00h and 63h. a value of 00h se ts the wiper of potentiometer 0 to its lowest position and 63h sets the wiper to its highest position. any hexadecimal value is a valid address. setting a value greater than the upper limit of the potentiomet er?s range, 64h or greater for potentiometer 0, will result in setting the wiper to its high est position, but the msb will be ignored. ds1845 8 of 14 2- wire protocol data transfer protocol figure 2 2-wire ac characteristics figure 3 ds1845 9 of 14 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +6.0v operating temperature - 40c to +85c; industrial programming temperature 0c to +70c storage temperature -55c to +125c soldering temperature see j-std-020 specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended operating conditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc +2.7 5.5 v 1 input logic 1 v ih .7 v cc v cc +0.5 v 1,3 input logic 0 v il -0.5 .3 v cc v 1,3 resistor inputs l,h,w -0.5 v cc +0.5 v 1 ds1845 10 of 14 dc electrical characteristics (-40c to +85c; v cc =2.7v to 5.5v) parameter symbol condition min typ max units notes supply current active i cc 0.5 ma 12,13 input leakage i li -1 +1 a wiper resistance 3v 5v r w 500 250 1000 600 wiper current i w 2 ma input logic levels a0, a1, a2 input logic 1 input logic 0 0.7 v cc -0.5 v cc +0.5 0.3 v cc v input current each i/o pin 0.4 ds1845 12 of 14 ac electrical characteristics (-40c to 85c , vcc=2.7v to 5.5v) parameter symbol condition min typ max units notes scl clock frequency f scl fast mode standard mode 0 0 400 100 khz 4 bus free time between stop and start condition t buf fast mode standard mode 1.3 4.7 s hold time (repeated) start condition t hd:sta fast mode standard mode 0.6 4.0 s 5 low period of scl clock t low fast mode standard mode 1.3 4.7 s high period of scl clock t high fast mode standard mode 0.6 4.0 s data hold time t hd:dat fast mode standard mode 0 0 0.9 s 6 data set-up time t su:dat fast mode standard mode 100 250 ns start set-up time t su:sta fast mode standard mode 0.6 4.7 s rise time of both sda and scl signals t r fast mode standard mode 20 + 0.1c b 300 1000 ns 7 fall time of both sda and scl signals t f fast mode standard mode 20 + 0.1c b 300 300 ns 7 set-up time for stop condition t su:sto fast mode standard mode 0.6 4.0 s capacitive load for each bus line c b 400 pf 7 eeprom write time t w 5 ms 8 notes : 1. all voltages are referenced to ground. 2. i stby specified with v cc equal 3.0v and 5.0v and control port logic pins are driven to the appropriate logic levels. appropriate logic levels specify that logic inputs are within a 0.5v of ground or v cc for the corresponding inactive state. 3. i/o pins of fast mode devices must not obstruct the sda and scl lines if v cc is switched off. 4. a fast mode device can be used in a st andard mode system, but the requirement t su:dat > 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250 ns before the scl line is released. 5. after this period, the first clock pulse is generated. 6. the maximum t hd:dat has only to be met if the devi ce does not stretch the low period (t low ) of the scl signal. ds1845 13 of 14 7. c b - total capacitance of one bus line in picofarads. timing referenced to 0.9v cc and 0.1v cc . 8. eeprom write begins after a stop condition occurs. 9. absolute linearity is used to measure expected wiper voltage as determined by wiper position. 10. relative linearity is used to determine the chan ge of wiper voltage between two adjacent wiper positions. 11. when used as a rheostat or va riable resister the temperature co efficient applies: 750 ppm/c. when used as a voltage divider or potentiometer, the effective temperature coefficient approaches 30 ppm/c. 12. i cc specified with sda pin open. 13. maximum icc is depend ent on clock rates. ds1845 14 of 14 ordering information ordering number package orerating temperature version pot 0/pot 1 ds1845e-010 14 pin tssop (173 mil) -40oc to +85oc 10 k 10 k ds1845e-010/t&r 14 pin tssop/tape & reel -40oc to +85oc 10 k 10 k ds1845x-010/t&r 14 pin flip chip -40oc to +85oc 10 k 10 k ds1845b-010 16 ball csbga (4x4 mm) -40oc to +85oc 10 k 10 k ds1845e-050 14 pin tssop (173 mil) -40oc to +85oc 10 k 50 k ds1845e-050/t&r 14 pin tssop/tape & reel -40oc to +85oc 10 k 50 k ds1845x-050/t&r 14 pin flip chip -40oc to +85oc 10 k 50 k ds1845b-050 16 ball csbga (4x4 mm) -40oc to +85oc 10 k 50 k ds1845e-100 14 pin tssop (173 mil) -40oc to +85oc 10 k 100 k ds1845e-100/t&r 14 pin tssop/tape & reel -40oc to +85oc 10 k 100 k ds1845x-100/t&r 14 pin flip chip -40oc to +85oc 10 k 100 k ds1845b-100 16 ball csbga (4x4 mm) -40oc to +85oc 10 k 100 k ds1845e-100+ 14 pin tssop lf (173 mil) -40oc to +85oc 10 k 100 k ds1845b-010+t&r 16 ball csbga/t&r lf (4x4 mm) -40oc to +85oc 10 k 10 k ds1845b-010/t&r 16 ball csbga/t&r -40oc to +85oc 10 k 10 k ds1845b-100+ 16 ball csbga lf (4x4 mm) -40oc to +85oc 10 k 100 k ds1845e-100+t&r 14 pin tssop/t&r lf (173 mil) -40oc to +85oc 10 k 0 k ds1845b-010+ 16 ball csbga lf (4x4 mm) -40oc to +85oc 10 k 0 k ds1845e-010+ 14 pin tssop lf ( 173 mil) -40oc to +85oc 10 k 0 k ds1845e-010+t&r 14 pin tssop/t& r lf -40oc to +85oc 10 k 0 k ds1845e-050+t&r 14 pin tssop/t&r lf (173 mil) -40oc to +85oc 10 k 0 k ds1845b-050+ 16 ball csbga lf (4x4 mm) -40oc to +85oc 10 k k ds1845e-050+ 14 pin tssop lf -40oc to +85oc 10 k 0 k ds1845b-020 16 ball csbga (4x4 mm) -40oc to +85oc 10 k 0 k ds1845b-050/t&r 16 ball csbga/t&r -40oc to +85oc 10 k 0 k ds1845b-050+t&r 16 ball csbga/t&r lf (4x4 mm) -40oc to +85oc 10 k 0 k ds1845e-020 14 pin tssop -40oc to +85oc 10 k 0 k *lf = lead free |
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